A semiconductor device such as a DRAM (Dynamic Random Access Memory) uses a triple-well structure in which three layers of wells are formed on a semiconductor substrate. For instance, the triple-well structure comprises a P-type semiconductor substrate, an N-type well (referred to as “deep N-well” hereinafter) formed on the P-type semiconductor substrate, and a P-type well (referred to as “P-well” hereinafter), electrically isolated from the P-type semiconductor substrate, in the N-type well (for instance, refer to Patent Documents 1 and 2).
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2000-058676A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2003-347421A